Customising a RISC-V Core
Presented at OSHCamp 2019.
Starting from an Open-source RISC-V core, add new instructions to it that you design! This workshop walks through the process of getting started with simulating an open-source RISC-V core and making the necessary modifications to decode and execute new instructions.
A processor that supports a new instruction is not much good if you can’t write any code for it, so the workshop also leads you through using the assembler to encode your new instructions, so that you can write programs using them and see that they execute correctly (or do not, and help you to work out the bugs in your implementation).
The tutorial materials provide enough of the implementation and sufficient guidance to be able to work through with a little experience of Verilog and C++. For those new to Verilog, the materials from last year’s talk and workshop (see below) provide a more accessible starting point.
- Introductory slides and accompanying notes
- Tutorial exercises
- RI5CY Core with worked solution
- Tutorial materials Github repo
- RI5CY Core starting point Github repo (new-instruction-base branch)
An Introduction to cycle-accurate Verilog simulation of open-source RISC-V cores
Presented at OSHCamp 2018.
Developing hardware designs in Verilog is tricky, for both FPGA platforms and ASIC hardware targets. Understanding the behaviour of a design, testing it, and debugging are made much easier by simulating in software. This tutorial gives a brief overview of approaches, focusing on cycle-accurate modelling, which is a relatively fast approach that is robustly implemented in an open-source tool called Verilator. The main focus is be on working with CPU designs, but the software and techniques are generally applicable to other areas.
The slides give a brief overview of how to use Verilator to simulate a design, to develop testbenches, and to visualise simulation output using GTKWave. The exercises begin with a simple Verilog example and walk through generating simulations of some popular open-source RISC-V cores. Although this tutorial focuses on simulation, the cores can in general be instantiated on FPGAs for use in real applications (and higher performance!)
Two different RISC-V implementations are used -Clifford Wolf’s PicoRV32 and RI5CY from the PuLP Platform. Loading and executing programs onto these bare metal systems through a testbench and also through a debugger (GDB) is be covered, along with some examples of interacting with the cores, and inspecting their state. Gathering accurate performance measurements is also possible, because the simulations are cycle-accurate.
The workshop should be of interest to people with a background in software who would like to tinker with open-source processor core development, and people with a background in hardware who would like to tinker with software toolchains.
The tutorial materials provide enough implementation that it is possible to follow this workshop without having had prior experience of hardware design or Verilog specifically – however, some understanding of programming and the organisation of computer hardware is required.
- Introduction to Verilator slides
- Verilog Refresher slides
- Tutorial code repository
- Exercise 1: Verilated Counter
- Exercise 2: RI5CY baremetal execution and Testbench
- Exercise 3: Driving RI5CY and PicoRV32 through a GDBServer
Accelerating Scientific Code with Numba
Presented at PyData London 2015 and PyCon UK 2015.